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TRF7970A
SLOS743K – AUGUST 2011 – REVISED APRIL 2014
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5.4
Handling Ratings
MIN
MAX
UNIT
T STG
Storage temperature range
-55
150
°C
V (ESD)
Electrostatic discharge
Human-Body Model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
(1)
-2
2
kV
Charged-Device Model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
Machine Model (MM)
-500
-200
500
200
V
V
(1)
(2)
5.5
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 2 kV
may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 500 V
may actually have higher performance.
Thermal Characteristics
PACKAGE
θ JC
θ JA (1)
POWER RATING (2)
T A ≤ 25°C T A ≤ 85°C
RHB (32 pin)
31°C/W
36.4°C/W
2.7 W
1.1 W
(1)
(2)
5.6
This data was taken using the JEDEC standard high-K test PCB.
Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to increase substantially.
Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-
term reliability.
Switching Characteristics
TYP operating conditions are T A = 25°C, VIN = 5 V, full-power mode (unless otherwise noted)
MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t LO/HI
DATA_CLK time high or low, one half of
DATA_CLK at 50% duty cycle
Depends on capacitive load on the I/O lines
(1)
250
62.5
50
ns
t STE,LEAD
t STE,LAG
Slave select lead time, slave select low to
clock
Slave select lag time, last clock to slave
select high
200
200
ns
ns
Slave select disable time, slave select
t STE,DIS
rising edge to next slave select falling
300
ns
edge
t SU,SI
t HD,SI
t SU,SO
t HD,SO
MOSI input data setup time
MOSI input data hold time
MISO input data setup time
MISO input data hold time
15
15
15
15
ns
ns
ns
ns
t VALID,SO
MISO output data valid time
DATA_CLK edge to MISO valid, C L ≤ 30 pF
30
50
75
ns
(1)
Recommended DATA_CLK speed is 2 MHz. Higher data clock depends on the capacitive load. Maximum SPI clock speed should not
exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output
resistance of 400 Ω (12-ns time constant when 30-pF load used).
10
Specifications
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